Ссылка на русскую версию / link to Russian version
FIFO is a key concept in hardware design. Understanding of FIFO is necessary for understanding the valid/ready protocol, which in turn is necessary for organisation of flow-control within a design.
Unfortunately, there are very few books on this topic, and to be fair, microarchitectural concepts are quite difficult to master from books, since understanding of these concepts are coming with practice. In other words it is more about developing hardware intuition.
The idea of the HDL training tool is that it can help develop a hardware intuition, providing the opportunity to explore ready-made scenarios in a step-by-step interactive way. The tool also provides detailed visualization of a simulated scenario.
Since the tool is a front-end for the HDL simulator, the real, synthesized SystemVerilog is executed on the simulator itself, which can be viewed and even modified.
So, the video of exploring FIFO on the training tool is here:
Link to Github where you can find how the training tool actually works and how to install it:
New scenarios will be added to the training tool. In particular, scenarios for exploring the valid/ready protocol will be added soon. Also scenarios that consider other elements of the flow-control organization - fifo, skid-buffers, credit-counters, registers, pipelines will be added as well.
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